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M41T56
Serial Real Time Clock with 56 bytes NVRAM
Feature summary
Counters for seconds, minutes, hours, day, date, month, years, and century 32 KHz crystal oscillator integrating load capacitance (12.5pF) providing exceptional oscillator stability and high crystal series resistance operation Serial interface supports I2C Bus (400kHz protocol) Ultra-low battery supply current of 450nA (typ@3V) 5V 10% supply voltage Timekeeping down to 2.5V Automatic power-fail detect and switch circuitry 56 bytes of general purpose RAM Software clock calibration to compensate crystal deviation due to temperature Automatic leap year compensation Operating temperature of -40 to 85C Packaging options include: - 28-lead SOIC and SNAPHAT(R) TOP (to be ordered separately) - SO8N
8 1
SO8N (M) 150mil width

SNAPHAT (SH) battery & crystal

28 1
SOH28 (MH)
October 2006
Rev 5
1/28
www.st.com 1
Contents
M41T56
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 2.3 2.4
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 3.2 3.3 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 5 6 7 8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
M41T56
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power down/up mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO8N - 8-pin plastic small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . 22 SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT, mech. data. . . . . . . . 23 SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data. . . . . . . 24 SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data. . . . . . 25 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SNAPHAT battery/crystal table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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List of figures
M41T56
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Acknowledge sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power down/up mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SO8N - 8-pin plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . . 23 SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 24 SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 25
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M41T56
Summary description
1
Summary description
The M41T56 is a low power, Serial Real Time Clock with 56 bytes of NVRAM. A built-in 32,768Hz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two-line, bi-directional bus. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T56 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. The energy needed to sustain the RAM and clock operations can be supplied from a small lithium coin cell. Typical data retention time is in excess of 10 years with a 50mAh, 3V lithium cell. The M41T56 is supplied in an 8-lead Plastic SOIC package or a 28-lead SNAPHAT(R) package. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4TxxBR12SH" (see Table 16 on page 26).
Caution:
Do not place the SNAPHAT battery/crystal package "M4Txx-BR12SH" in conductive foam as this will drain the lithium button-cell battery. Figure 1. Logic diagram
VCC VBAT
OSCI SCL M41T56
OSCO SDA FT/OUT
VSS
AI02304B
5/28
Summary description Table 1.
OSCI OCSO FT/OUT SDA SCL VBAT VCC VSS
M41T56 Signal names
Oscillator Input Oscillator Output Frequency Test / Output Driver (Open Drain) Serial Data Address Input / Output Serial Clock Battery Supply Voltage Supply Voltage Ground
Figure 2.
8-pin SOIC connections
OSCI OSCO VBAT VSS
M41T56 8 1 2 7 3 6 4 5
AI02306B
VCC FT/OUT SCL SDA
Figure 3.
28-pin SOIC connections
NC NC NC NC NC NC NC NC NC NC NC NC NC VSS 28 1 2 27 3 26 4 25 5 24 6 23 7 22 M41T56 8 21 9 20 10 19 11 18 12 17 13 16 14 15
AI03607
VCC NC FT/OUT NC NC NC NC NC SCL NC NC NC SDA NC
6/28
M41T56 Figure 4.
OSCI OSCILLATOR 32.768 kHz OSCO FT/OUT VCC VSS VBAT VOLTAGE SENSE and SWITCH CIRCUITRY DIVIDER
Summary description Block diagram
1 Hz SECONDS MINUTES CENTURY/HOURS DAY DATE MONTH CONTROL LOGIC YEAR CONTROL
SCL
SERIAL BUS INTERFACE
RAM (56 x 8) ADDRESS REGISTER
SDA
AI02566
7/28
Operation
M41T56
2
Operation
The M41T56 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order: 1. 2. 3. 4. 5. 6. 7. 8. 9. Seconds register Minutes register Century/hours register Day register Date register Month register Years register Control register RAM
The clock continually monitors VCC for an out of tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When VCC falls below VBAT, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to VCC at VBAT and recognizes inputs when VCC goes above VPFD volts.
2.1
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the state of the data line, from High to Low, while the clock is High, defines the START condition.
8/28
M41T56
Operation
2.1.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Figure 5. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
9/28
Operation Figure 6. Acknowledge sequence
M41T56
START SCLK FROM MASTER 1 2 8
CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
Figure 7.
SDA tBUF
Bus timing requirements sequence
tHD:STA tR tF
tHD:STA
SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO
AI00589
10/28
M41T56 Table 2.
Symbol fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT tHD:DAT
(2)
Operation AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) Data setup time Data hold time STOP condition setup time Time the bus must be free before a new transmission can start 4 4.7 250 0 4.7 4.7 Min 0 4.7 4 1 300 Max 100 Unit kHz s s s ns s s ns s s s
tSU:STO tBUF
1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
2.2
READ mode
In this mode, the master reads the M41T56 slave after setting the slave address (see Figure 8 on page 12 and Figure 9 on page 12). Following the WRITE Mode Control Bit (R/W = 0) and the Acknowledge Bit, the word address An is written to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ Mode Control Bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Bit. The M41T56 slave transmitter will now place the data byte at address An + 1 on the bus. The master receiver reads and acknowledges the new byte and the address pointer is incremented to An + 2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. An alternate READ mode may also be implemented, whereby the master reads the M41T56 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer, see Figure 10 on page 12.
11/28
Operation Figure 8. Slave address location
R/W
M41T56
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 9.
READ mode sequence
START START R/W R/W
BUS ACTIVITY: MASTER SDA LINE
S
ACK
WORD ADDRESS (n)
S
ACK ACK
DATA n
ACK
DATA n+1
ACK
AI00899
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
STOP
DATA n+X
P
NO ACK
Figure 10. Alternative READ mode sequence
START
BUS ACTIVITY: MASTER SDA LINE
S
ACK
R/W
DATA n
ACK
DATA n+1
ACK ACK
DATA n+X
P
NO ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00895
12/28
STOP
M41T56
Operation
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T56 slave receiver. Bus protocol is shown in Figure 11 on page 13. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41T56 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see Figure 8 on page 12).
2.4
Data retention mode
With valid VCC applied, the M41T56 can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the M41T56 will automatically deselect, write protecting itself when VCC falls between VPFD (max) and VPFD (min). This is accomplished by internally inhibiting access to the clock registers and SRAM. When VCC falls below the Battery Back-up Switchover Voltage (VSO), power input is switched from the VCC pin to the battery and the clock registers and SRAM are maintained from the attached battery supply. All outputs become high impedance. On power up, when VCC returns to a nominal value, write protection continues for tREC. For a further more detailed review of battery lifetime calculations, please see Application Note AN1012. Figure 11. WRITE mode sequence
START
BUS ACTIVITY: MASTER SDA LINE
R/W
S
ACK
WORD ADDRESS (n)
ACK
DATA n
ACK
DATA n+1
ACK
DATA n+X
P
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
13/28
STOP
Clock operation
M41T56
3
Clock operation
The eight byte clock register (see Table 3) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, Minutes, and Hours are contained within the first three registers. Bits D6 and D7 of Clock Register 2 (Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 3 contain the Day (day of week). Registers 4, 5, and 6 contain the Date (day of month), Month, and Years. The final register is the Control Register (this is described in the Clock Calibration section). Bit D7 of Register 0 contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The seven Clock Registers may be read one byte at a time, or in a sequential block. The Control Register (Address location 7) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be delayed by 250ms to allow the READ to be completed before the update occurs. This will prevent a transition of data during the READ.
Note:
This 250ms delay affects only the clock register update and does not alter the actual clock time. Table 3.
Address D7 0 1 2 3 4 5 6 7
1. Keys:
S = SIGN Bit FT = FREQUENCY TEST Bit ST = STOP Bit OUT = Output level X = Don't care CEB = Century Enable Bit CB = Century Bit
Register map(1)
Data D6 D5 10 Seconds 10 Minutes CB X X X 10 years OUT FT S 10 hours X X X D4 D3 D2 D1 D0 Function/range BCD format Seconds Minutes 00-59 00-59
ST X CEB(2) X X X
Seconds Minutes Hours Day Date Month Years Calibration
Century/hours 0-1/00-23 Day Date Month Year Control 01-07 01-31 01-12 00-99
10 date X 10 M.
2. When CEB is set to '1,' CB toggles from '0' to '1' or from '1' to '0' every 100 years (dependent upon the initial value set). When CEB is set to '0,' CB does not toggle.
14/28
M41T56
Clock operation
3.1
Clock calibration
The M41T56 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M41T56 improves to better than 2 ppm at 25C. The oscillation rate of any crystal changes with temperature (see Figure 12 on page 16). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome "trim" capacitors. The M41T56 design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12 on page 16. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit Calibration Byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register (Addr 7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minutes cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T56 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accessed the Calibration Byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit in the Control Register, is set to a '1,' and the oscillator is running at 32,768Hz, the FT/OUT pin of the device will toggle at 512Hz. Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024Hz would indicate a +20ppm oscillator frequency error, requiring a -10(XX001010) to be loaded into the Calibration Byte for correction.
Note:
Setting or changing the Calibration Byte does not affect the Frequency Test output frequency.
15/28
Clock operation Figure 12. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T -T )2 O F K = -0.036 ppm/C2 0.006 ppm/C2 TO = 25C 5C
M41T56
Temperature C
AI00999b
Figure 13. Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
3.2
Output driver pin
When the FT Bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the Control Register. In other words, when D6 of location 7 is a '0' and D7 of location 7 is a '0' and then the FT/OUT pin will be driven low.
Note:
The FT/OUT pin is open drain which requires an external pull-up resistor.
3.3
Initial power-on defaults
Upon initial application of power to the device, the FT Bit will be set to a '0' and the OUT Bit will be set to a '1.' All other Register bits will initially power-on in a random state.
16/28
M41T56
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol TA TSTG TSLD(1)(2) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation SNAPHAT SOIC Value -40 to 85 -40 to 85 C -55 to 125 260 -0.3 to 7 -0.3 to 7 20 0.25 C V V mA W Unit C
1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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DC and AC parameters
M41T56
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 5. Operating and AC measurement conditions(1)
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
Value 4.5 to 5.5 -40 to 85 100 5 0 to 3 1.5
Unit V C pF ns V V
Figure 14. AC measurement I/O Waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 6.
Symbol CIN COUT tLP
(3)
Capacitance
Parameter(1)(2) Input capacitance (SCL) Output capacitance (SDA, FT/OUT) Low-pass filter input time constant (SDA and SCL) 0.25 Min Max 7 10 1 Unit pF pF s
1. Effective capacitance measured with power supply at 5V; sampled, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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M41T56 Table 7.
Symbol ILI ILO ICC1 ICC2 VIL VIH VOL VBAT(2) IBAT
DC and AC parameters DC characteristics
Parameter Input leakage current Output leakage current Supply current Supply current (standby) Input low voltage Input high voltage Output low voltage Battery supply voltage Battery supply current TA = 25C, VCC = 0V, oscillator ON, VBAT = 3V IOL = 5mA, VCC = 4.5V 2.5 3 450 Test condition(1) 0V VIN VCC 0V VOUT VCC Switch frequency = 100kHz SCL, SDA = VCC - 0.3V -0.3 3 100 1.5 VCC + 0.8 0.4 3.5 550 Min Typ Max 1 1 300 Unit A A A A V V V V nA
1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V (except where noted). 2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
Table 8.
Symbol fO RS CL
Crystal Electrical Characteristics
Parameter(1)(2)(3) Resonant frequency Series resistance Load capacitance 12.5 Min Typ 32.768 60 Max Unit kHz k pF
1. These values are externally supplied if using the SO8N package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T56. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. All SNAPHAT battery/crystal tops meet these specifications.
Figure 15. Power down/up mode AC Waveforms
VCC VPFD VSO tPD SDA SCL tFB tRB tREC
IBAT DATA RETENTION TIME
AI00595
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DC and AC parameters Table 9.
Symbol tPD tFB tRB tREC
M41T56 Power down/up mode AC characteristics
Parameter(1) Min 0 300 100 10 Max Unit ns s s s
SCL and SDA at VIH before power down VPFD (min) to VSS VCC fall time VSS to VPFD (min) VCC rise time SCL and SDA at VIH after power up
1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V (except where noted).
Table 10.
Symbol VPFD VSO
Power down/up trip points DC characteristics
Parameter(1)(2) Power-fail deselect voltage Battery back-up switchover voltage Min 1.2 VBAT Typ 1.25 VBAT VBAT Max 1.285 VBAT Unit V V
1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V (except where noted).
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M41T56
Package mechanical information
6
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical information Figure 16. SO8N - 8-pin plastic small package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
M41T56
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 11.
Symbol
SO8N - 8-pin plastic small outline, package mechanical data
millimetres Typ Min Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 - 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 - 0.020 8 0.050 Typ inches Min Max 0.069 0.010
A A1 A2 b c ccc D E E1 e h k L L1
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M41T56
Package mechanical information Figure 17. SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
1. Drawing is not to scale.
Table 12.
SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT, mech. data
mm inches Max 3.05 0.05 2.34 0.36 0.15 17.71 8.23 1.27 - 3.20 11.51 0.41 0 28 0.10 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8
Symb Typ A A1 A2 B C D E e eB H L Min
N CP
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Package mechanical information
M41T56
Figure 18. SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
1. Drawing is not to scale.
Table 13.
SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data
mm inches Max 9.78 6.73 6.48 7.24 6.99 0.38 0.46 21.21 14.22 15.55 3.20 2.03 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 .6122 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 .6280 0.142 0.090
Symb Typ A A1 A2 A3 B D E eA eB L Min
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M41T56
Package mechanical information Figure 19. SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline
A1 A2 A A3
eA D
B eB
L
E
SHTK-B
1. Drawing is not to scale.
Table 14.
SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data
mm inches Max 10.54 8.00 7.24 8.51 8.00 0.38 0.46 21.21 17.27 15.55 3.20 2.03 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 .6122 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 .6280 0.142 0.090
Symb Typ A A1 A2 A3 B D E eA eB L Min
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Part numbering
M41T56
7
Part numbering
Table 15.
Example:
Ordering information scheme
M41T 56 M 6 E
Device type M41T
Supply voltage and write protect voltage 56 = VCC = 4.5 to 5.5V
Package M = SO8N MH(1)= SOH28
Temperature range 6 = -40 to 85C
Shipping method For SO8N: E = Lead-free package (ECOPACK(R)), tubes F = Lead-free package (ECOPACK(R)), tape & reel For SOH28: E = Lead-free package (ECOPACK(R)), tubes F = Lead-free Package (ECOPACK(R)), tape & reel
1. The SOIC package (SOH28) requires the SNAPHAT(R) battery package which is ordered separately under the part number "M4Txx-BR12SHx" in plastic tube or "M4Txx-BR12SHxTR" in Tape & Reel form (see Table 16).
Caution:
Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. Table 16. SNAPHAT battery/crystal table
Description Lithium battery (48mAh)/crystal SNAPHAT Lithium battery (120mAh)/crystal SNAPHAT Package SH SH
Part number M4T28-BR12SH M4T32-BR12SH
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M41T56
Revision history
8
Revision history
Table 17.
Date March 1999 12/23/99 03/21/00 11/30/00 01/25/01 02/16/01 04/06/01 07/17/01 08/02/02 11/07/02 15-Jun-04
Document revision history
Rev. # 1.0 1.1 1.2 1.3 1.4 2.0 2.1 2.2 2.3 2.4 3.0 First issue SOH28 package added Series resistance Max Value changed (Table 8) Added PSDIP8 package Corrected graphic, measurements of PSDIP8 (Figure 18, Table 14) Reformatted, table added (Table 16) Add temp./voltage information to characteristics (Table 7, Table 2); correct Series Resistance (Table 8) Basic formatting changes Modify reflow time and temperature footnote (Table 4); modify Crystal Electrical Characteristics table footnotes (Table 8); removed PSDIP8 package Correct figure name (Feature summary on page 1) Reformatted; add Lead-free information; update characteristics (Figure 12; Table 4, Table 15) Changed document to new template; amalgamated diagrams in Feature summary on page 1; amended footnotes in Table 3: Register map; updated Package mechanical data in Section 6: Package mechanical information; small text changes for entire document, removed lead packages from Table 15, ECOPACK compliant Updated package mechanical data in Figure 16.: SO8N - 8-pin plastic small package outline. Revision details
11-Sep-2006
4
09-Oct-2006
5
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M41T56
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